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BitsExplorer finds what people are building with AI, every day. See today's picks →
Chip layouts designed at VSCLAB, UC Riverside — 27 designs from RTL to GDS-II across ASAP7 7nm, SAED32, Nangate45, SKY130 and GF180MCU, with Synopsys Fusion Compiler, OpenLane and OpenROAD.
Description excerpted from the original listing, which is linked below.
Every Monday: how many projects were built with AI that week, which tools built them, where they came from, and the week's picks.
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