USIL Research Map
Interactive paper explorer, classifications, analytics, and community pull requests
BitsExplorer finds what people are building with AI, every day. See today's picks →
Integer STDP continual-learning core for FPGA (Python golden model + Verilog). Tiny-net co-sim. IMU/power carrier PCB. Tables are simulator results. Not an ASIC.
Description excerpted from the original listing, which is linked below.
Every Monday: how many projects were built with AI that week, which tools built them, where they came from, and the week's picks.
Read the latest week