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Sparse Memory Lm

A 21M-parameter LM with a 16.8M-row product-key memory: as good as a 114M dense model and runs with the table on an SSD. Triton kernels for ROCm and CUDA.

Description excerpted from the original listing, which is linked below.

Open it Source code

Facts

Published: 3 Oct 2026 (15d ago)
Medium: web
Language: English (the page says so itself)
First seen: 5 Oct 2026, 19:55 UTC

Built with

Claude Code: confirmed
the agent's own trailer in the repository's commit history

What we can see

68 hygiene score

Certificate issued by YR1, 26 days remaining
Cookie attributes no cookies set
Credentials and payment does not ask for either
No strict transport security
Served over HTTPS
Mail authentication neither published
No insecure resources
Redirects none
Security headers 1 of 5 set, policy permits inline or evaluated script
Third-party origins 3
Transport security TLS 1.3

Observed 5 Oct 2026 by fetching the page as a browser would. This describes hygiene and transparency, not safety: a missing header does not make a site dangerous, and a complete set does not make it trustworthy.

Made this?

Show it on your own site or README. It links back to this page.

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For a web page

<a href="https://bitsexplorer.com/i/1893315/sparse-memory-lm"><img src="https://bitsexplorer.com/badge/1893315.svg" alt="Featured on BitsExplorer" height="22"></a>

For a README (Markdown)

[![Featured on BitsExplorer](https://bitsexplorer.com/badge/1893315.svg)](https://bitsexplorer.com/i/1893315/sparse-memory-lm)

Changes we have seen

5 Oct 2026 first indexed

Sparse Memory Lm

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